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low cost, precision analog front end and controller for battery test/formation systems data sheet AD8451 f eatures integrated constant current and voltage mode s with automatic switchover charge and d ischarge modes precision voltage and current measurement integrated precision control feedback blocks precision interface to pwm or linear power con verters fixed g ain settings current sense gain: 26 v/v (typ) voltage sense gain: 0.8 v/v (typ) e xcellent ac and dc p erformance m aximum offset voltage drift : 0. 9 v/c m aximum gain drift : 3 ppm/c low current sense amplifier input voltage noise : 9 nv/ hz typ current sense cmrr: 108 db min ttl c ompliant l ogic applications battery cell formation and testing battery module testing general description t he ad845 1 is a precision analog front end and controller for testing and monitoring battery cells . a p recision fixed gain instrumentation amplifier (ia) measure s the battery charge/ discharge current , and a fixed gain difference amplifier (da) measures the battery voltage (see figure 1 ). internal l aser trimmed resistor networks set the gains for the ia and the da, optimiz ing the performance of the AD8451 over the rated temperature range . the ia gain is 26 v/v and the da gain i s 0.8 v/v . voltages at the iset and vset inputs set the desired constant current (c c ) and constant voltage (c v ) values. cc to cv sw i tching i s automatic and transparent to the system. a ttl logic level input , mode, selects the c h arge or discharge mode ( high for charge , and low for discharge ) . a n analog output , vctrl, interfaces directly with the analog devices, inc., adp1972 pulse - width modulation (pwm) controller . th e AD8451 simplifies designs by providing excellent accuracy, performance over temperature, flexibility with functionality, and overall reliability in a space - saving package. the AD8451 is available in an 80 - lead , 14 mm 14 mm 1 .40 mm lqfp a nd is rated for an operating temperature of ?40 c to +85c . functional block dia gram current sense i a vo lt age sense d a isme a iset bvmea vset vint mux isvn isvp bvn bvp vint vctrl 1 mode ad 8451 ive0/ive1 vve0/ vve1 (charge/ discharge) switching vvp 0 vsetbf vclp vcln bvrefh/ bvref l isrefh/ isref l vref 0.8 voltage reference cons t ant vo lt age loo p fi l ter cons t ant current loo p fi l ter 2 6 12137-001 figure 1. rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by an alog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent righ ts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com
AD8451 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typica l performance characteristics ............................................. 9 ia characteristics ......................................................................... 9 da characteristics ..................................................................... 11 cc and cv loop filter amplifiers, and vset buffer .......... 13 vint buffer ................................................................................ 15 reference characteristics .......................................................... 16 theory of operation ...................................................................... 17 overview ...................................................................................... 17 instrumentation amplifier (ia) ............................................... 18 difference amplifier (da) ........................................................ 19 cc and cv loop filter amplifiers .......................................... 19 mode pin, char ge and discharge control ........................... 21 applications information .............................................................. 22 functional description .............................................................. 22 power supply connections ....................................................... 23 current sense ia connections ................................................. 23 voltage sense da connections ................................................ 23 battery current and voltage control inputs (iset and vset) ....................................................................................................... 23 loop filter amplifiers ............................................................... 24 connecting to a pwm controller (vctrl pin) ...................... 24 step - by - step design example ................................................... 24 evaluation board ............................................................................ 26 introduction ................................................................................ 26 features and tests ....................................................................... 26 evaluating the AD8451 .............................................................. 27 schematic and artwork ............................................................. 28 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 3 / 14 revision 0: initial version rev. 0 | page 2 of 32
data sheet AD8451 specifications avc c = + 15 v, avee = ?15 v; dvcc = + 5 v; t a = 25c, unless otherwise noted. table 1 . parameter test condition s /comments min typ max unit current sense i nstrumentation a mplifier internal fixed gain 26 v/v gain error v ismea = 10 v 0.1 % ga in drift t a = t min to t max 3 ppm/c gain nonlinearity v ismea = 10 v , r l = 2 k? 3 ppm offset voltage (rti) isrefh and isrefl pins grounded ?1 1 0 + 1 1 0 v offset voltage drift t a = t min to t max 0.9 v/c input bias current 15 30 na temperature coefficient t a = t min to t max 1 5 0 pa/c input offset current 2 na temperature coefficient t a = t min to t max 1 0 pa/c input common - mode voltage range v isvp ? v isvn = 0 v avee + 2.3 avcc ? 2.4 v over temperature t a = t min to t max avee + 2.6 avc c ? 2.6 v overvoltage input range avcc ? 55 avee + 55 v differential input impedance 150 g? input common - mode impedance 150 g? output voltage swing avee + 1.5 avcc ? 1. 2 v over temperature t a = t min to t max avee + 1.7 avcc ? 1. 4 v capaciti ve load drive 1000 pf short - circuit current 40 ma reference input voltage range isrefh and isrefl pins tied together avee avcc v reference input bias current v isvp = v isvn = 0 v 5 a output voltage level shift isrefl pin grounded maximum isref h pin connected to vref pin 1 7 20 23 mv scale factor v ismea /v isrefh 6.8 8 9.2 mv/v common - mode rejection ratio ( cmrr ) v cm = 2 0 v 108 db temperature coefficient t a = t min to t max 0.01 v/v/ c power supply rejection ratio ( psrr ) v s = 20 v 108 122 db voltage noise f = 1 khz 9 nv/hz voltage noise , peak to peak f = 0.1 hz to 10 hz 0.2 v p -p current noise f = 1 khz 80 fa/hz current noise , peak to peak f = 0.1 hz to 10 hz 5 pa p -p small signal ?3 db bandwidth 1.5 mhz slew rate v ismea = 10 v 5 v/s voltage sense d ifference a mplifer internal fixed gains 0.8 v/v gain error v in = 10 v 0. 1 % gain drift t a = t min to t max 3 ppm/c gain nonlinearity v bvmea = 10 v, r l = 2 k? 3 ppm offset voltage (rto) bvrefh and bvrefl pins grounded 500 v offset voltage drift t a = t min to t max 4 v/c differential input voltage range v bvn = 0 v, v bvrefl = 0 v ?16 +16 v input common - mode voltage range v bvmea = 0 v ?27 +27 v differential input impedance 200 k? input common - mode impedance 90 k? output voltage swing avee + 1.5 avcc ? 1.5 v over temperature t a = t min to t max avee + 1.7 avcc ? 1.7 v capacitive load drive 1000 pf short - circuit current 30 ma rev. 0 | page 3 of 32
AD8451 data sheet parameter test condition s /comments min typ max unit reference input voltage range bvrefh and bvrefl pins tied together avee avcc v output voltage level shift bvrefl pin grounded maximum bvrefh pin connected to vref pin 4 .5 5 5.5 mv scale factor v bvmea /v bvrefh 1.8 2 2.2 mv/v cmrr v cm = 10 v, rto 80 db temperature coefficient t a = t min to t max 0.05 v/v/c psrr v s = 20 v, rto 100 db output voltage noise f = 1 khz, rti 105 nv/hz voltage noise, peak to peak f = 0.1 hz to 10 hz, rti 2 v p -p small signal ?3 db bandwidth 1 mhz slew rate 0.8 v/s constant current and constant voltage loop filter amplifiers offset voltage 150 v offset voltage drift t a = t min to t max 0.6 v/c input bias cu rrent ?5 +5 na over temperature t a = t min to t max ?5 +5 na input common - mode voltage range avee + 1.5 avcc ? 1.8 v output voltage swing v vcln = avee + 1 v, v vclp = avcc ? 1 v avee + 1.5 avcc ? 1 v over temperature t a = t min to t max avee + 1.7 av cc ? 1 v closed - loop output impedance 0.01 ? capacitive load drive 1000 pf source short - circuit current 1 ma sink short - circuit current 40 ma open - loop gain 140 db cmrr v cm = 10 v 100 db psrr v s = 20 v 100 db voltage noise f = 1 khz 10 nv/hz voltage noise, peak to peak f = 0.1 hz to 10 hz 0.3 v p -p current noise f = 1 khz 80 fa/hz current noise, peak to peak f = 0.1 hz to 10 hz 5 pa p -p small signal gain bandwidth product 3 mhz slew rate v vint = 10 v 1 v/ s cc to cv transition time 1.5 s vint and constant voltage buffer nominal gain 1 v/v offset voltage 150 v offset voltage drift t a = t min to t max 0.6 v/c input bias current cv buffer only ?5 +5 na over temperature t a = t min to t ma x ?5 +5 na input voltage range avee + 1.5 avcc ? 1.8 v output voltage swing current sharing and constant voltage buffers avee + 1.5 avcc ? 1.5 v over temperature t a = t min to t max avee + 1.7 avcc ? 1.5 v vint buffer v vcln ? 0.6 v vclp + 0. 6 v over temperature t a = t min to t max v vcln ? 0.6 v vclp + 0.6 v output clamps voltage range vint buffer only vclp pin v vcln avcc ? 1 v vcln pin avee + 1 v vclp v closed - loop output impedance 1 ? capacitive load drive 1000 pf short - cir cuit current 40 ma psrr v s = 20 v 100 db rev. 0 | page 4 of 32
data sheet AD8451 parameter test condition s /comments min typ max unit voltage noise f = 1 khz 10 nv/hz voltage noise, peak to peak f = 0.1 hz to 10 hz 0.3 v p -p current noise f = 1 khz, cv buffer only 80 fa/hz current noise, peak to peak f = 0.1 hz to 10 hz 5 pa p -p small signal ?3 db bandwidth 3 mhz slew rate v out = 10 v 1 v/s voltage reference nominal output voltage with respect to agnd 2.5 v output voltage error 1 % temperature drift t a = t min to t max 10 ppm/c line regulation v s = 1 0 v 40 ppm/v load regulation i vref = 1 ma (source only) 400 ppm/ma output current, sourcing 10 ma voltage noise f = 1 khz 100 nv/hz voltage noise, peak to peak f = 0.1 hz to 10 hz 5 v p -p digital interface, mode input mode pin (pin 39) input voltage high, v ih with respect to dgnd 2.0 dvcc v input voltage low, v il with respect to dgnd dgnd 0.8 v mode switching time 500 ns power supply operating voltage range avcc 5 36 v avee ?31 0 v analog supply range avcc ? avee 5 36 v dvcc 3 5 v quiescent current avcc 7 10 ma avee 6.5 10 ma dvcc 40 70 a temperature range for specified performance ?40 +85 c operational ?55 +125 c rev. 0 | page 5 of 32
AD8451 data sheet absolute maximum rat ings table 2 . p arameter rating analog supply voltage (avcc ? avee) 36 v digital supply voltage ( dvcc ? dgnd ) 36 v maximum voltage at any input pin avcc minimum voltage at any input pin avee operating temperature range ? 40 c to + 8 5c storage temperature range ?65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operation al section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance the ja value assumes a 4 - layer jedec standard board with zero airflow. table 3 . thermal resistance package type ja unit 80- lead lqfp 54.7 c/w esd caution rev. 0 | page 6 of 32
data sheet AD8451 pin configuration an d function descripti ons vctr l vcln a vcc vve1 nc vint vcl p vve0 nc vvp0 vset nc dvcc nc dgnd nc nc vref nc vsetbf nc = no connec t . do not connect t o this pin. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 nc nc nc isref l isrefls agnd isrefh vref a vee isme a a vcc nc isrefb iset nc ive0 ive1 nc vint a vee bvps nc nc bv p nc bvrefh agnd bvref l bvrefls nc bvn nc bvns nc bvme a a vcc mode nc vref a vee 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AD8451 t o p view 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 17 18 19 20 1 1 59 58 57 54 55 56 60 53 52 51 49 48 47 46 45 44 43 42 41 50 isv p rg p nc nc nc nc nc nc nc nc nc rgn isvn nc nc nc nc nc nc nc pin 1 indentfier 12137-002 figure 2 . pin configuration table 4 . pin function descriptions pin no. nemonic in put /ut put 1 description 1, 20 isvp, isvn input current s ense i nstrumentation a mplifier p ositive ( n oninverting) and n egative ( i nverting) i np ut s . connect these pins across the current sense shunt resistor. 2, 19 rgp, rgn n / a negative i nput of the preamplifiers of the c urrent s ense i nstrumentation a mplifier . 3 to 18, 21, 23, 25, 31, 33, 34, 40, 41, 43, 44, 46, 48, 52, 55, 63, 66, 69, 78 to 80 nc n/a no connect. do not connect to this pin. 22, 35 bvps, b v ns input kelvin sense pins for the bvp and bvn voltage sense difference amplifier inputs. 24, 32 bvp, bvn input voltage sense difference amplifier inputs. 26, 42, 73 vref output voltage refe rence output pins. vref = 2.5 v. 27 bvrefh input reference input for the voltage sense difference amplifier. to level shift the voltage sense difference amplifier output by approximately 5 mv, connect this pin to the vref pin. otherwise, connect this pin to the bvrefl pin. 28, 75 agnd n/a analog ground pins. 29 bvrefl input reference input for the voltage sense difference amplifier. the default connection is to ground. 30 bvrefls input kelvin sense pin for the bvrefl pin. rev. 0 | page 7 of 32
AD8451 data sheet pin no. mnemonic in put /out put 1 description 36, 61, 72 avee n/a analog neg ative supply pins. the default voltage is ?15 v. 37 bvmea output voltage sense difference amplifier output. 38, 57, 70 avcc n/a analog positive supply p ins. the d efault voltage is 15 v. 39 mode input ttl compliant l ogic input select s charge or discharge mode. low = discharge, high = charge . 45 dgnd n/a digital ground pin. 47 dvcc n/a digital s upply. the d efault voltage is 5 v. 49 vset input target voltage for the voltage sense control loop. 50 vsetbf output buffered voltage vset. 51 vvp0 input noni nverting input of the voltage sense integrator for discharge mode. 53 vve0 input inverting input voltage for the voltage sense integrator for discharge m ode. 54 vve1 input inverting input of the voltage sense integrator for charge mode. 56, 62 vint outp ut minimum output of the voltage sense and current sense integrator amplifiers. 58 vcln input low clamp voltage for vctrl. 59 vctrl output controller output voltage. connect this pin to the input of the pwm controller (for example, the comp pin of the adp1972 ). 60 vclp input high clamp voltage for vctrl. 64 ive1 input inverting input of the current sense integrator for charge mode. 65 ive0 input inverting input of the current sense integrator for discharge mode. 67 iset input target voltage for the current sense control loop. 68 isrefb output buffered voltage isrefl. 71 ismea output current sense instrumentation amplifier output. 74 isrefh input reference input for the current sense amplif ier. to level shift the current sense instrumentation amplifier output by approximately 20 mv, connect this pin to the vref pin. otherwise, connect this pin to the isrefl pin. 76 isrefl input reference input for the current sense amplifier. the default co nnection is to ground. 77 isrefls input kelvin sense pin for the isrefl pin. 1 n/a means not applicable. rev. 0 | page 8 of 32
data sheet AD8451 typical performance characteristics av cc = + 1 5 v, avee = ? 1 5 v, t a = 25c, and r l = , unless otherwise noted. ia c haracteristics 1 5 o u tp u t v o lt a g e (v) 3 0 0 2 0 2 5 2 0 2 5 1 0 3 0 0 5 ?5 ?5 ?10 ?10 1 5 1 0 5 a vcc = +25v a vee = ?5v input common-mode vo lt age (v) 12137-003 figure 3 . input common - mode voltage vs. output voltage for avcc = +25 v and avee = ?5 v 1 5 ?1 5 ?1 0 ? 5 0 5 1 0 ?3 5 ?3 0 ?1 0 ?2 0 0 4 5 3 0 4 0 2 0 1 0 ?2 5 ? 5 ?1 5 5 3 5 2 5 1 5 i n p u t curr e n t ( ma ) i n p u t v olt a g e (v) a v cc = + 25 v a vee = ?5 v 12137-004 figure 4 . input overvoltage performance for avcc = +25 v and avee = 5 v 17.0 16.8 16.6 16.4 16.2 16.0 15.8 15.6 15.4 15.2 15.0 ?15 ?10 ?5 0 5 10 15 20 25 input bias current (na) input common-mode vo lt age (v) a vcc = +15v a vee = ?15v a vcc = +25v a vee = ?5v 12137-005 figure 5 . input bias current vs. input common - mode voltage 20 ?20 ?15 ?10 ?5 0 5 10 15 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode vo lt age (v) output vo lt age (v) a vcc = +15 v a vee = ?15 v 12137-006 figure 6 . input common - mode voltage vs. output voltage for avcc = +15 v and avee = 15 v 1 5 ?1 5 ?1 0 ? 5 0 5 1 0 ?45 ?35 ?40 ?30 ?10 ?20 0 45 30 40 20 10 ?25 ?5 ?15 5 35 25 15 input current (ma) input vo lt age (v) a vcc = +15v a vee = ?15v 12137-007 figure 7 . input overvoltage performance for avcc = +15 v and avee = 15 v 20 19 18 17 16 15 14 13 12 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 input bias current (na) temper a ture (c) ?i b +i b 12137-008 figure 8 . input bias current vs. temperature rev. 0 | page 9 of 32
AD8451 data sheet 2 0 ?1 0 0 ? 8 0 ? 6 0 ? 4 0 ? 2 0 0 ? 4 0 ? 3 0 ? 2 0 ? 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 gain error (v/v) temper a ture (c) 12137-009 figure 9. gain error vs. temperature 0 . 3 ? 0 . 3 ? 0 . 2 ? 0 . 1 0 0 . 1 0 . 2 ? 4 0 ? 3 0 ? 2 0 ? 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 cmrr (v/v) temperature (c) a v c c = + 2 5 v a vee = ? 5 v 12137-010 figure 10 . normalized cmrr vs. temperature g a i n ( d b ) 1 m frequenc y (hz) 10 0 k 1 0 k 1 0 m 10 0 2 0 4 0 1 0 3 0 5 0 1 k 0 ? 2 0 ? 1 0 a vcc = +15v a vee = ?15v 12137-0 1 1 figure 11 . gain vs. frequency 16 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 0 . 1 1 1 0 10 0 100 k 10 k 1 k c m rr ( d b ) f r e q u e nc y ( h z) 12137-012 f igure 12 . cmrr vs. frequency 16 0 0 6 0 4 0 2 0 8 0 10 0 12 0 14 0 1 1 0 10 0 1 m 100 k 10 k 1 k ps rr ( d b ) f r e q u e nc y ( h z) a vee a vcc 12137-013 figure 13 . psrr vs. frequency 10 0 1 1 0 0 . 1 1 1 0 10 0 100 k 10 k 1 k spe c t ra l d e n s it y v olt a g e n oi se ( n v/ h z) f r e q u e nc y ( h z) r t i 12137-014 figure 14 . spectral density voltage noise , rti vs. frequency rev. 0 | page 10 of 32
data sheet AD8451 da characteristics 60 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?10 ?5 0 5 10 15 20 25 30 input common-mode vo lt age (v) output vo lt age (v) 12137-015 a vcc = +25v a vee = ?5v figure 15 . input common - mode voltage vs. output voltage for avcc = +25 v and avee = ?5 v 0 ?50 ?40 ?30 ?20 ?10 100 1k 10k 100k 1m v alid for al l r a ted supp l y vo lt ages gain (db) frequenc y (hz) 12137-016 figure 16 . gain vs. frequency 0 ?120 ?100 ?80 ?60 ?40 ?20 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) v alid for al l r a ted supp l y vo lt ages 12137-017 figure 17 . cmrr vs. frequency 50 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode vo lt age (v) output vo lt age (v) 12137-018 a vcc = +15v a vee = ?15v 50 ?200 ?150 ?100 ?50 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 gain error (ppm) temper a ture (c) 12137-019 figure 19 . gain error vs. temperature 3 ?3 ?2 ?1 0 1 2 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 cmrr (v/v) temper a ture (c) 12137-020 figure 20 . normalized cmrr vs. temperature rev. 0 | page 11 of 32
AD8451 data sheet 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10 100 100k 10k 1k frequenc y (hz) psrr (db) v alid for al l r a ted supp l y vo lt ages a vee a vcc 12137-021 figure 21 . psrr vs. frequency 1k 10 100 0.1 1 10 100 100k 10k 1k spectra l densit y vo lt age noise (nv/hz) frequenc y (hz) rti 12137-022 figure 22 . spectral density voltage noise , rti vs. frequency rev. 0 | page 12 of 32
data sheet AD8451 c c and cv loop filter amplifiers, and vset buffer 500 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 ?15 ?10 ?5 0 5 10 15 20 25 input offset voltage (v) input common-mode voltage (v) avcc = +25v avee = ?5v avcc = +15v avee = ?15v 12137-023 figure 23 . input offset voltage vs. input common - mode voltage for two supply voltage combinations 100 0 10 20 30 40 50 60 70 80 90 ?15 ?10 ?5 0 5 10 15 20 25 input bias current (pa) input common-mode voltage (v) avcc = +25v avee = ?5v avcc = +15v avee = ?15v 12137-024 figure 24 . input bias current vs. input common - mode voltage for two supply voltage combinations 100 ?40 ?20 0 20 40 60 80 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 input bias current (na) temperature (c) ?i b +i b 12137-025 figure 25 . input bias current vs. temperature 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 output source current (ma) temperature (c) constant current loop and constant voltage loop amplifiers avcc = +25v avee = ?5v avcc = +15v avee = ?15v 12137-026 figure 26 . output source current vs. temperature for two supply voltage combinations 120 ?40 ?20 0 20 40 60 80 100 ?45.0 ?225.0 ?202.5 ?180.0 ?157.5 ?135.0 ?112.5 ?90.0 ?67.5 10 100 1k 10k 100k 1m 10m open-loop gain (db) phase (degrees) frequency (hz) phase gain 12137-027 figure 27 . open - loop gain and phase vs. frequency 160 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) cons t ant current loo p and cons t ant vo lt age loo p fi l ter amplifiers 12137-028 figure 28 . cmrr vs. frequency rev. 0 | page 13 of 32
AD8451 data sheet 140 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m psrr (db) frequency (hz) +psrr ?psrr 12137-029 figure 29 . psrr vs. frequency 1k 1 10 100 0.1 1 10 100 100k 10k 1k spectral density voltage noise (nv/hz) frequency (hz) 12137-030 figure 30 . range of spectral density voltage noise vs. frequency for the op amps and buffers 1.5 ?1.5 ?0.5 0.5 1.0 ?1.0 0 ?15 35 30 25 20 15 10 5 0 ?5 ?10 output voltage (v) time (s) transition avcc = +15v avee = ?15v iset vctrl 12137-031 figure 31 . cc to cv transition rev. 0 | page 14 of 32
data sheet AD8451 vint buffer 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 output voltage swing (v) temperature (c) vctrl output with respect to vclp vctrl output with respect to vcln vclp and vcln reference valid for all rated supply voltages 12137-032 figure 32 . output voltage swing with respect to vclp and vcln vs. temperature 15 ?15 ?10 ?5 0 5 10 100 1m 100k 10k 1k load resistance () output voltage swing (v) 12137-033 temp = ?40c temp = +25c temp = +85c vcl p vcln figure 33 . output voltage swing vs. load resistance at three temperatures 6 ?1 0 1 2 3 4 5 10 40 35 30 25 20 15 output current (ma) clamped output voltage (v) vcl p vcln v in = +6v/?1v temp = ?40c temp = 0c temp = +25c temp = +85c 12137-034 figu re 34 . clamped output voltage vs. output current at four temperatures 6 ?1 0 1 2 3 4 5 0 40 35 30 25 20 15 10 5 time (s) output voltage (v) c l = 100pf r l = 2k 12137-035 figure 35 . large signal transient response, r l = 2 k, c l = 100 pf 0.20 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 10 9 8 7 6 5 4 3 2 1 time (s) output voltage (v) c l = 10pf c l = 100pf c l = 510pf c l = 680pf c l = 1000pf 12137-036 figure 36 . small signal transient response vs. capacitive load 100 10 1 0.1 10 100 1k 10k 100k 1m output impedance () frequency (hz) 12137-037 figure 37 . output impedance vs. frequency rev. 0 | page 15 of 32
AD8451 data sheet reference characteri stics 2.51 2.50 2.49 2.48 2.47 2.46 0 1 2 3 4 5 6 7 8 9 10 output voltage (v) output current?sourcing (ma) t a = ?40c t a = +25c t a = ?20c t a = +85c t a = 0c avcc = +25v avee = ?5v 12137-038 figure 38 . output voltage vs. output current (sourcing) over temperature 2.9 2.8 2.7 2.6 2.5 2.4 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 output voltage (v) output current?sinking (ma) t a = +85c t a = +25c t a = 0c t a = ?20c t a = ?40c avcc = +25v avee = ?5v 12137-039 figure 39 . output voltage vs. output current (sinking) over temperature 1200 1100 1000 900 800 700 600 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 load regulation (ppm/ma) temperature (c) avcc = +25v avee = ?5v 12137-040 figure 40 . source and sink load regulation vs. temperature 1k 10 100 0.1 1 10 100 100k 10k 1k spectral density voltage noise (nv/hz) frequency (hz) 12137-041 figure 41 . spectral density voltage noise vs. frequency rev. 0 | page 16 of 32
data sheet AD8451 theory of operation overview t o form and test a battery, the battery must undergo charge and discharge cycles. during these cycles, the battery terminal current and voltage must be precisely controlled to prevent battery failure or a reduction in the capacity of the battery . therefore, battery formation and test systems require a high precision analog front end to monitor the battery current and terminal voltage. the analog front end of the AD8451 includes a precision current sense fixed gain instrumentation amplifier ( ia ) to measure the battery current and a precision voltage sense fixed gain difference amplif ier ( da ) to measure the battery voltage. battery formation and test systems charge and discharge batteries using a constant current/constant voltage (cc/cv) algorithm. in other words, the system first forces a set constant current in to or out of the batter y until the battery voltage reaches a target value. at this point, a set constant voltage is forced across the battery terminals. the AD8451 provides two control loops cc loop and a cv loop that tr ansition automatically after the battery reaches the user defined target voltage. these loops are implemented via two precision specialty amplifiers with external feedback networks that set the transfer function of the cc and cv loops. moreover, in the AD8451 , these loops reconfigure themselves to charge or discharge the battery by toggling the mode pin. figure 42 is a block diagram of the AD8451 that illustrates the distinct sections of th e AD8451 , including the ia and da measurement blocks, and the loop filter amplifiers . figure 43 is a block diagram of a battery formation and test system. 17 18 15 16 8 7 6 5 4 3 2 14 13 9 12 11 10 isvp mode mode rgp nc nc nc nc nc nc nc nc nc nc nc nc nc rgn isvn nc 19 34 35 27 25 24 23 22 21 33 32 31 30 29 59 54 56 60 53 51 49 44 43 41 50 58 46 39 ? + ? + ? + ? + ? + a vee a vee 1 1 1 20 42 37 40 26 28 36 38 57 55 52 47 48 45 nc isrefh nc vref isrefls isrefl nc ive1 ismea ive0 iset vint isrefb nc nc agnd avee avcc nc avee vctrl vcln vve1 vint vclp vve0 vvp0 vset nc nc nc nc vsetbf vref avcc avcc nc nc dvcc nc dgnd 64 62 69 65 68 67 73 71 78 74 77 76 80 79 61 63 70 72 75 66 bvrefh bvps nc bvrefl bvp nc nc bvns bvrefls nc nc nc bvmea bvn nc mode vref agnd avee avcc vint buffer vset buffer 10k 20k 19.2k 100k 100 80k 79.9k nc +/? +/? nc 50k 100k 10k 1667 806 100k 10k 10k cv loo p fi l ter amplifier cc loo p fi l ter amplifier b a tte r y current sensing i a b a tte r y vo lt age sensing d a cons t ant current and vo lt age loo p fi l ter amplifiers ? + AD8451 1.1m a 2.5v vref isref l buffer 1 12137-042 figure 42 . detailed block diagram rev. 0 | page 17 of 32
AD8451 data sheet battery vctr l sense resis t or isv p isvn bv p bvn mode switches (3) ba tte r y current avee cv buffer cons t ant current loo p fi l ter amplifier ? + ? + 1 vint buffer vsetbf vset iset v1 v2 c d c d c d vint isme a bvme a vve1 vve0 vvp0 ive1 ive0 da ? + ? + ia AD8451 controller 1 s e t b at t e ry v o l t a ge s e t b at t e ry c ur re nt externa l p assive compens a tion network c = charge d = discharge cons t ant volt age loo p fi l ter amplifier power converter switched or linear system loo p compens a tion 12137-043 figure 43 . signal path of a n li - ion battery f ormation and test system u sing the AD8451 instrumentation ampl ifier (ia) figure 44 is a block diagram of the ia , which is used to monitor the battery current. the architecture of the ia is the classic 3 - op - amp topology , similar to the analog devices industry - standard ad8221 and ad620 , with a fixed gain of 26. this ar chitecture provides the highest achievable cmrr at a given gain, enabling high - side battery current sensing without the introduction of significant errors in the measurement. for more information about instrumentation amplifiers, see a designer's guide to instrumentation amplifiers . reversing polarity when charging and discharging figure 43 shows that during the charge cycle, the power converter feeds current into the battery, generating a positive voltage across the current sense resistor. during the discharge cycle, the power converter draws current from the battery, generating a negative voltage across the sense resistor. in other words, the b attery current polarity reverses when the battery discharges. in the c c control loop, this change in polarity can be problematic if the polarity of the target current is not reversed. to solve this problem, the AD8451 ia includes a multiplexer preceding its inputs that inverts the polarity of the ia gain. this multiplexer is controlled via the mode pin. when the mode pin is logic high (charge mode), the ia gain is noninverting, and when the mode pin is logic low (discharge mode), the ia gain is inverting. 10k 20k 806 i a rg p rgn isvn isv p +current shunt ?current shunt isme a ? + g = 2 subtrac t or 100k 19.2k isrefh isref l vref polarit y inverter polarity inverter mode ? + ? + 10k 10k 10k 1667 12137-044 figure 44 . ia simplified block diagram ia offset option as shown in figure 44 , the ia reference node is connected to the isrefl and isrefh pins via an internal resistor divider. this resistor divider can be used to introduce a temperature insensitiv e offset to the output of the ia such that i t always reads a voltage higher than zero for a zero differential input. b eca use the output voltage of the ia is always positive, a unipolar analog - to - digital converter ( adc ) can digitize it. rev. 0 | page 18 of 32
data sheet AD8451 when the isrefh pin is tied to the vref pin with the isrefl pin grounded , the voltage at the ismea pin is increased by 20 m v, guaranteeing that the outp ut of the ia is always positive for zero differential inputs. other voltage shifts can be realized by tying the isrefh pin to an external voltage source. the gain from the isrefh pin to the ismea pin is 8 m v / v. for zero offset, tie the isrefl and isrefh pi ns to ground. battery reversal and overv oltage protection the AD8451 ia can be configured for high - side or low - side current sensing. if the ia is configured for high - side current sensing (see figure 43 ) and the battery is connected backward, the ia inputs may be held at a voltage that is below the negative power rail (avee) , depending on the battery voltage . to prevent damag e to the ia under these conditions, the ia inputs include overvoltage protection circuitry that allow s them to be held at voltages of up to 55 v from the opposite power rail. in other words, the safe voltage span for the ia inputs extends from avcc ? 55 v to avee + 55 v. differen ce amplifier (da) figure 45 is a block diagram of the da , which is used to monitor the battery voltage. the architecture of the da is a subtractor amplifier with a fixed gain of 0.8 . th i s gain value allow s the da to funnel the voltage of a 5 v batter y to a level that can be read by a 5 v adc with a 4.096 v reference . bvref l bv p bvn 100k 100k 100k 50k 80k 79.9k da ? + bvrefh vref bvme a 12137-045 figure 45 . da simplified block diagram the resistors that form the da gain network are laser trimmed to a m atching level better than 0.1%. this level of matching minimizes the gain error and gain error drift of the da whi le maximizing the cmrr of the da . this match ing also allows the controller to set a stable target voltage for the battery over temperature wh ile rejecting the ground bounce in the battery negative terminal. like the ia, the da can also level shift its output voltage via an in ternal resistor divider that is tied to the d a reference node. this resistor divider is connected to the bvrefh and bvref l pins . when the bvrefh pin is tied to the vref pin with the bvrefl pin grounded , the voltage at the bvmea pin is increased by 5 m v, guaranteeing that the output of the da is always positive for zero differential inputs. other voltage shifts can be realiz ed by tying the bvrefh pin to an external voltage source. the gain from the bvrefh pin to the bvmea pin is 2 m v / v. for zero offset, tie the bvrefl and bvrefh pins to ground. cc and cv loop filte r amplifiers the cc and cv loop filter amplifiers are high pre cision, low noise specialty amplifiers with very low offset voltage and very low input bias current. thes e amplifiers serve two purposes: ? using external components, the amplifiers implement active loop filters that set the dynamics (transfer function) of t he cc and cv loops. ? the amplifiers perform a seamless transition from cc to cv mode after the battery reaches its target voltage . figure 46 is the functional block diagram of the ad845 1 cc and cv feedback loops for charge mode (mode logic pin is high). for illustration purposes, the external networks connected to the loop amplifiers are simple rc networks configured to form single - pole inverting integrators. the outputs of the cc and cv loop filter amplifiers are coupled to the vint pin s via an analog nor circuit (minimum output selector circuit) , such that they can only pull the vint node down. in other words, the loop amplifier that requires the lowest volt age at the vint pin s is in control of the node. thus, only one loop amplifier, cc or cv, can be in control of the system charging control loop at a ny given time. rev. 0 | page 19 of 32
AD8451 data sheet iset ? + ? + cc loo p amplifier cv loo p amplifier ive1 vve1 analog ?nor ? isvn bv p bvn g da ? + ? + g ia ismeas bvme a i ba t ia da v2 r2 c2 vset r 1 c 1 1 vctr l vcln vcl p vint buffer v1 v ba t sense resis t or mode 5v ? + r s vint power converter vint iout isv p vctr l current power bus minimum output selec t or v4 v3 v3 < vctr l < v4 12137-046 figure 46 . functional block diagram of the cc and cv loops in ch arge mode (mode pin high) the unity - gain amplifier ( vint b uffer ) buffers the vint pin s and drives the vctrl pin . the vctrl pin is the control output of the ad845 1 and the control input of the pow er converter. the v iset and v vset v oltage sources set the target constant current and the target constant voltage , respectively. when the cc and cv feedback loops are in a steady state, the charging current is set at i bat_ss = s ia iset r g v i bat_ss = is the steady state charging current. g ia is the ia gain. r s is the value of the shunt resistor. t he target voltage is set at v bat_ss = da vset g v here v bat_ss = steady state battery voltage. g da is the da gain. because the offse t voltage of the loop amplifiers is in series with the target voltage sources , v iset and v vset , the high precision of these amplifiers minimizes this source of error. figure 47 shows a typical cc/cv charging profile for a li - ion b attery . in the first stage of the charging process, the battery is charged with a cc of 1 a. when the battery voltage reaches a target voltage of 4.2 v, the charging process transitions such that the battery is charged with a cv of 4.2 v. the following ste ps describe how the ad845 1 implements the cc/cv charging profile (see figure 46 ). in this scenario, the battery begins in the fully discharged state , and t he system has just been turned on such that i bat = 0 a at time 0. 1. because the voltages at the ismea and bvmea pins are less than the target voltages (v iset and v vset ) at time 0, both integrators begin to ramp, increasing the voltage at the vint node. 1 . 2 5 0 0 . 2 5 0 . 5 0 0 . 7 5 1 . 0 0 5 0 1 2 3 4 0 5 4 3 2 1 curr e n t ( a ) v ol t a g e (v) ti me (h ou rs) c c char g e b egi n s t ran sition f r o m cc to c v c c char g e ends 12137-047 fi gure 47 . representative constant current to constant voltage transition n ear the e nd of a battery charging cy cl e 2. as the voltage at the vint node increases, the voltage at the vcrtl node rises, and the output current of the power co nverter, i bat , increases (assum ing that an increasing voltage at the vcrtl node increases the output current of the power converter). 3. when the i bat current reaches the cc steady state value, i bat_ss , the battery voltage is still less than the target steady state value , v bat_ss . therefore, the cv loop tries to keep pulling the vint node up while the cc loop tries to keep it at its current voltage . a t this point , the voltage at the ismea pin equals v iset ; therefore, the cc loop stops integrating. 4. because the loop amplifiers can only pull the vint node down due to the analog nor circuit, the cc loop takes control of the charging feedback loop , and the cv loop i s disabled. 5. as the charging process continues, the battery voltage increases until it reaches the stea dy state value , v bat_ss , and the voltage at the bvmea pin reaches the target voltage , v vset . rev. 0 | page 20 of 32
data sheet AD8451 6. t he cv loop tries to pull the vint node down to reduce the charging current ( i bat ) and prevent the battery voltage from rising any further. at the same time, th e cc loop tries to keep the vint node at its current voltage to keep the battery current at i bat_ss . 7. because the loop amplifiers can only pull the vint node down due to the analog nor circuit, the cv loop takes control of the charging feedback loop , and th e cc loop is disabled. the analog nor (minimum output selector ) circuit that coup les the outputs of the loop amplifiers is optimized to minimize the transition time from cc to cv control . any delay in the transition cause s the cc loop to remain in control of the charge feedback loop after the battery voltage reache s its target value. therefore, the battery voltage continue s to rise beyond v bat_ss until the control loop transitions ; that is, the battery voltage overshoot s its target voltage. when the cv loop takes control of the charge feedback loop, it reduces the battery voltage to the target voltage. a large overshoot in the battery voltage due to transition delays can damage the battery; thus, it is crucial to minimize delays by implementi ng a fast cc to cv transition. figure 48 is the functional block diagram of the AD8451 cc and cv feedback loops for discharge mode (mode logic pin is low). in discharge mo de, the feedback loops operate in a similar manner as in charge mode. the only difference is in the cv loop amplifier, which operates as a noninverting integrator in discharge mode. for illustration purposes, the external networks connected to the loop amp lifiers are simple rc networks configured to form single - pole integrators (see figure 48). compensation in battery formation and test systems, the cc and cv feedback loops have significantly different open - loop gai n and crossover frequencies; therefore, each loop requires its own frequency compensation. the active filter architecture of the AD8451 cc and cv loops allows the frequency response of each loop to be set independently via external components. moreover, due to the internal switches in the cc and cv amplifiers, the frequency response of the loops in charge mode does not affect the frequency response of the loops in discharge mode. unlike simpler cont rollers that use passive networks to ground for frequency compensation, the AD8451 allows the use of feedback networks for its cc and cv loop filter amplifiers. these networks enable the implementa tion of both proportional differentiator ( pd ) type ii and proportional integrator differentiator ( pid ) type iii compensators. note that in charge mode, both the cc and cv loops implement inverting compensators, whereas in discharge mode, the cc loop implem ents an inverting compensator , and the cv loop implements a noninverting compensator. as a result, the cv loop in discharge mode includes an additional amplifier, vset buffer, to buffer the vset node from the feedback network (see figure 48 ). vint buffer the unity - gain amplifier (vint buffer) is a clamp amplifier that drives the vctrl pin. the vctrl pin is the control output of the AD8451 and the control inp ut of the power converter (see figure 46 and figure 48 ). the output voltage range of this amplifier is bounded by the clamp voltages at the vclp and vcln pins such that v vc ln ? 0.5 v < v vctrl < v vclp + 0.5 v the reduction in the output voltage range of the amplifier is a safety feature that allows the AD8451 to drive devices such as the adp1972 pwm controller, whose input voltage range must not exceed 5.5 v (that is, the voltage at the comp pin of the adp1972 must be below 5.5 v). mode pin, charge an d discharge control the mode pin is a ttl logic input that configures the AD8451 for either charge or discharge mode. a logic low (v mode < 0.8 v) corresponds to discharge mode, and a logic high (v m ode > 2 v) corresponds to charge mode. internal to the AD8451 , the mode pin toggles all single - pole, double throw ( spdt ) switches in the cc a nd cv loop amplifiers and inverts the gain polarity of t he ia. vset vset buffer vsetbf iset ? + ? + cc loo p amplifier cv loo p amplifier ive0 vve0 analog ?nor ? isvn bv p bvn g da ? + ? + g ia ismeas bvme a i ba t ia da r2 r2 c2 vvp0 r1 c1 c 2 1 vctr l vcln vcl p vint buffer v1 v ba t sense resis t or mode ? + r s vint vint isv p minimum output selec t or v4 v3 v3 < vctr l < v4 v2 1 12137-048 power converter iout vctr l current power bus figure 48 . functional block diagram of the cc and cv loops in discharge mode (mode pin low) rev. 0 | page 21 of 32
AD8451 data sheet applications information this section describes how to use the ad845 1 in the context of a battery formation and test system. this section includes a design example of a small scale model of an actual system . functional descripti on the AD8451 is a precision analog front end and controller for battery formation and test systems. these systems use precision controllers and power stages to put batteries through charge and discharge cycles. figure 49 shows the signal path of a simplified switch ing battery formation and test system using the AD8451 controller and the adp1972 pwm controller . for more informa tion on the adp1972 , see the adp1972 data sheet. the AD8451 is suitable for systems that form and te st nicad, nimh, and li - ion batteries and is designed to operate in conjunction with both linear and switching power stages. the AD8451 includes the following blocks (see fi gure 42 and the theory of operation section for more information). ? a f ixed ga in ia that senses low - side or high - side battery current. ? a f ixed gain da that measures the terminal voltage of the battery . ? two loop filter error amplif iers that receive the battery target current and voltage and establish the dynamics of the cc and cv feedback loops. ? a m inimum output selector circuit that combines the outputs of the loop filter error amplifiers to perform automatic cc to cv switching. ? an o utput clamp amplifier that drives the vctrl pin. the voltage range of this amplifier is limited by the voltage at the vclp and vcln pins such that it cannot over range the subsequent stage. the output clamp amplifier can drive switching and linear power c onverters. note that a n increas ing voltage at the vctrl pin must translate to a larger output current in the power converter. ? a 2.5 v reference whose output node is the vref pin . a l ogic input pin ( mode ) that changes the configuration of the controller fro m charge to discharge mode. a logic high at the mode pin configures charge mode ; a logic low configures discharge mode. battery leve l shifter vctr l sense resis t or isv p isvn bv p bvn mode switches (3) a vcc output drivers ba tte r y current avee cv buffer cons t ant current loo p fi l ter amplifier ? + ? + 1 vint buffer vsetbf vset iset c d c d c d vint isme a bvme a vve1 vve0 vvp0 ive1 ive0 output fi l ter da ? + ? + ia AD8451 controller 1 s e t b at t e ry v o l t a ge s e t b at t e ry c ur re nt dc- t o-dc power converter externa l p assive compens a tion network c = charge d = discharge cons t ant volt age loo p fi l ter amplifier adp1972 pwm 12137-049 figure 49 . complete signal path of a battery test or formation system suitable for li - ion batteries rev. 0 | page 22 of 32
data sheet AD8451 po wer supply connectio ns the AD8451 requires two analog power supplies (avcc and avee), one digital power supply (dvcc), one analog ground (agnd), and one digital ground (dgnd). avcc and avee power a ll the analog blocks, including the ia, da, and op amps , and dvcc powers the mode input logic. agnd provides a reference and return path for the 2.5 v reference, and dgnd provides a reference and return path for the digital circuitry. the rated absolute ma ximum value for avcc ? avee is 36 v, and the minimum operating avcc and avee voltages are +5 v and ?5 v, respectively. due to th e high psrr of the AD8451 analog blocks, avcc can be connected direct ly to the high current power bus (the input voltage of the power converter) without risking the injection of supply noise to the controller outputs. a commonly used power supply combination is + 1 5 v for avc c , ? 1 5 v for avee, and +5 v for dvcc . the + 1 5 v ra il for avcc provides enough headroom to the ia such that it can be connected in a high - side current sensing configuration. the ? 1 5 v rail for avee allows the da to sense accidental reverse battery conditions (see the reverse batter y conditions section). connect decoupling capacitors to all the supply pins. a 1 f capacitor in parallel with a 0.1 f capacitor is recommended. c urrent sense ia connections for a description of the ia , see the t heory of operation section , figure 42 , and figure 44. the ia fixed gain is 26. current sens ors t wo common options for current sens ors are isolated current sensing transduc ers and shunt resist ors . isolated current sensing transducers are galvanic al ly isolat ed from the power converter and are affected less by the high frequency noise generated by switch mode power supplies. shunt resistors are less expensive and easier to dep loy. if a shunt resistor sensor is used, a 4 - terminal , low resistance shunt resistor is recommended. two of the four terminals conduct the battery current , whereas the other two terminals conduct virtually no current . the terminals that conduct no current are sense terminals that are used to measure the voltage drop across the resistor (and, therefore, the current flowing through it) using an amplifier such as the ia of the AD8451 . to interface the ia with the current sensor, connect the sense terminals of the sensor to the isvp and isvn pins of the AD8451 (see figure 50). optional low - pass fil ter the AD8451 is designed to control both linear regulators and switching power converters. linear regulators are generally noise free, whereas switch mode power converters generate switching nois e. connecting an external differential low - pass filter betwe en the current sensor and the ia inputs reduces the injectio n of switching noise into the ia (see figure 50). isv p ? + 10k 20k 20k 10k lpf rg p 4 termina l shunt i ba t ? + dut isvn rgn + ? 10k 10k 1667 12137-050 figure 50 . 4 - terminal shunt resis tor c onnected to the current sense ia v oltage s ense da connections for a description of the da , see the theory of operation section, figure 42 , and figure 45 . the da fixed gain is 0.8. reverse battery conditions the output voltage of the AD8451 da can be us ed to detect a reverse battery connection. a ? 1 5 v rail for avee allows the output of the da to go below ground when the battery is connected backward. therefore, the condition can be detected by monitoring the bvmea pin for a negative voltage . battery cur rent and voltage control inputs (iset and vset) the voltage s at the iset and vset input pins set the target battery current and voltage for the cc and cv loops. these inputs must be driven by a precision voltage source (or a digital - to - analog converter [ da c ] connected to a precision reference) whose output voltage is referenced to the same voltage as the ia and da reference pins (is refh/isrefl and bvrefh/bvrefl , respectively) . for example, if the ia ref erence pin s are connected to agnd, the voltage source c onnected to iset must also be referenced to agnd. in the same way , if the da reference pin s are connected to agnd, the voltage source connected to vset must also be referenced to agnd. in constant current mode, when the cc feedback loop is in a steady stat e, the iset input sets the battery current as follows: i bat_ss = s ia iset r g v s iset r v 26 where: g ia is the ia gain. r s is the value of the shunt resistor. rev. 0 | page 23 of 32
AD8451 data sheet in constant voltage mode, when the cv feedback loop is in steady state, t he vset input sets the battery voltage as follows: v bat_ss = da vset g v = 8 . 0 vset v here g da is the da gain. therefore, the accuracy and temperature stability of the formation and test system are not only dependent on the precisi on of the AD8451 , but also on the accuracy of the iset and vset inputs. loop filter amplifie r s the ad845 1 has two loop filter amplifiers , also known as error amplifiers (see figure 49 ). one amplifier is for constant current control (cc loop filter amplifier), and the other amplifier is for constant voltage control (cv loop filter amplifier). the outp uts of these amplifiers are combined using a minimum output selector circuit to perform automatic cc to cv switching. table 5 lists the inputs of the loop filter amplifiers for charge mode and discharge mode. table 5 . integrator input connection s feedback loop function reference input feedback terminal control the current while discharging a battery is et ive0 control the current while charging a battery iset ive1 contr ol the voltage while discharging a b attery vset vve0 control the voltage while charging a battery vset vve1 t he cc and cv amplifiers in charge mode and the cc amplifier in discharge mode are inverting integrators, whereas the cv amplifier in discharge mode is a noninverting integrator. th erefore, the cv amplifier in discharge mode uses an extra amplifier, the vset buffer , to buffer the vset input pin (see figure 42) . in addition , the cv amplifier in discharge mode uses the vvp0 pin to couple the si gnal from the bvmea pin to the integrator. connectin g to a pwm controller ( vctrl pin ) the vctrl output pin of the AD8451 is designed to interface with linear power converters and with pwm controlle rs such as the adp1972 . the voltage range of the vctrl output pin is bound by the voltages at the vclp and vcln pins, as follows: v vcln ? 0.5 v < v vctrl < v vclp + 0.5 v because the maximum rated i nput voltage at the comp pin of the adp1972 is 5.5 v , connect th e clamp voltages of the output amplifier to 5 v (vclp) and ground (vcln) to prevent over - ranging of the comp input. as an additional prec aution, install an external 5.1 v z ener diode from the comp pin to ground with a series 1 k resistor connected between the vctrl and comp pins . consult the adp1972 data sheet for additional applications information. given the architecture of the AD8451 , the controller requires that an increasing voltage at the vctrl pin translate s to a larger output current in the power converter. if this is not the case, a unity - gain inverting amplifier can be added in series with the AD8451 ou tput to add an extra inversion. step - by - step design example this section describes the systematic design of a 1 a battery charger/discharger using the ad845 1 controller and the adp1972 pwm controller. the power converter used in this design is a nonisolated buck boost dc - to - dc converter. the target battery is a 4.2 v fully charged, 2.7 v fully discharged li - ion batter y. step 1: design the switching power converter select the switches and passive components of the buck boost power converter to support the 1 a maximum battery current. the design of the power converter is beyond the sc ope of this d ata sheet ; however, there are many application notes and other helpful documents available from manufacturers of integrated driver circuits and power mosfet output devices that can be used for reference. step 2: identify the control voltage ra nge of the adp1972 the control voltage range of the adp1972 (voltage range of the comp input pin) is 0.5 v to 4.5 v. an input voltage of 4.5 v results in the highest duty cycle and output current, wh ereas an input voltage of 0.5 v results in the lowest duty cycle and output current. because the comp pin connects directly to the vctrl output pin of the AD8451 , the battery current is proportional to the voltage at the vctrl pin . for information about how to interface the adp1972 to the power converter switches, see the adp1972 data sheet. step 3: determine the control vol tage for the cv loop the relationship between the control voltage for the cv loop (the voltage at the vset pin), the target battery voltage, and the da gain is as follows: cv battery target voltage = 8 . 0 vset da vset v g v = rev. 0 | page 24 of 32
data sheet AD8451 step 4: determine the control voltage for the cc loop and the shunt resistor the relationship between the control voltage for the cc loop (the voltage at the iset pin ), the target battery current , and the ia gain is as follows: cc ba ttery target current = s iset s ia iset r v r g v = 26 the voltage across the shunt resistor is as follows: shunt resistor voltage = 26 iset ia iset v g v = step 5: choose the control voltage sources the input control voltages (the voltages at the iset and vset pins ) can be generated by an analog voltage source such as a vol tage reference or by a dac. in both cases, select a device that provides a stable , low noise output voltage. if a dac is preferred , analog devices offers a wide range of precision converters. for example, the ad5668 16- bit dac provides up to eight 0 v to 4 v sources when connected to an external 2 v reference. to maximize accuracy, the control voltage sources must be referenced to the same potential as the outputs of the ia and da . for example, if the ia and da reference pins are connected to agnd, connect the reference p ins of the control voltage sources to agnd. step 6: select the compensation devices feedback controlled switching power converters require frequency compensation to guarantee loop stability. there are many references available about how to design the compe nsation for such power converters. the ad845 1 provides active loop filter error amplifiers for the cc and cv control loops that can implement proportional integrator ( pi ) , pd, and pid compensators using external passive components. rev. 0 | page 25 of 32
AD8451 data sheet evaluation board introduction the AD8451 - e va l z evaluation board is a convenient standalone platform for evaluating the major elements of the AD8451 , e ither as a standalone component or connected to a battery test/formation system. in the latter configuration, the AD8451 - e va l z operates just as i t would within a system including the pwm and dc - to - dc power converter. simply connect the current and voltage sense voltages from the system directly to the board terminus. th is feature is used when setting or evaluating loop compensation using a field of passive compensation components. figure 51 is a photograph of the AD8451 - e va l z . features and tests sma connectors provide access for input voltages to the sensitive i nstrumentation (ia) and difference (da) amplifiers. isvp and isvn connectors are the ia inputs, and bvp and bvn are the da inputs. these inputs accept the dc voltages from battery current and voltage measurement sources, or from a precision dc voltage sour ce. sma connectors iset and vset are available for precision dc control voltages for cc or cv battery charging voltages. sma isreflo is available for applying a nonzero reference voltage to the ia. sma vctrl connects to the input of a dc - to - dc power conver ter as seen in figure 52 . convenient test loops are provided connecting scope probes or instruments for the remainder of the input/output . the mode switch selects between the charge and discharge option . figure 52 is a schematic of the AD8451 - e va l z . table 6 lists and describes the various switches and functions . 12137-051 figure 51 . photograph of the AD8451 - evalz rev. 0 | page 26 of 32
data sheet AD8451 table 6 . AD8451 - evalz test switches and functi ons switch function operation default position mode selects the c harge or the d ischarge mode . the mode switch selects chg (logic high) or disch (logic low). chg run_test1 selects between the user inputs and the 2.5 v AD8451 reference voltage. the AD8451 operates normally when the run_test1 switch is in the run position. when in the test position, 2.5 v is applied to the iset and vset inpu ts. run run_test2 tests the cc or cv loop filter amplifiers. the voltage at the vctrl output (tpvctrl) for all positions is 0 v when run_test1 is in run position and 2.5 v when run_test1 in test position. run isref _ hi the isref_hi switch connects pin 74 (isrefh) to the internal 2.5 v reference (2.5 position ) or to the sma connector ext (the external input for a user defined vref input). when in the 2.5v position, the isref_hi switch connects pin 74 (isrefh, an internal 100 k ? resistor) to pin 73 (vref, t he 2.5 v reference). when the isref_lo switch is in the norm position, the output at pin 71 (ismea) shifts positive by 20 mv. ext isref _ lo connects pin 76 (isrefl) to ground (norm) or to the isrefl sma input connector. when in the norm position and the is ref_hi switch is in the ext position, there is no offset applied to the ismea output. when in the ext position , the isreflo sma is selected. norm evaluating the AD8451 test the instrumentation a mplifier connect the tpisvn jumper to ground, and then apply 100 mv dc to tpisvp. measure 2.6 v at the tpismea output. subtract any offset voltages from the output reading before calculating the gain. 20 mv offset at imeas output connect a jumper from tpi svp to tpisvn to ground by using another jumper and any one of the convenient black test loops. measure 0 v 2.86 mv at the tpismea output ( that is, the ia residual offset voltage multiplied by gain). move the isreflo switch to the ext position , and the i srefhi switch to the 20 mv ( ext ) position . the output will then increase by 20 m v. test the difference amplifier insert a shorting jumper at h eader gnd_bvn. with 1 v dc applied to tpbvp, m easure 0.8 v at tpbvmea . for the most accurate gain measurement, su btract the offset voltage from the output voltage before calculating gain. 5 mv offset at bvmeas output insert jumpers in the gnd_bvp and gnd_bvn headers. measure 0 v 0.4mv at the tpbvmea output (that is, the da residual offset voltage multiplied by gain ). connect a jumper between tpbrefh and tp 2.5v. the output will then increase by 5 m v. cc and cv integrator tests switches run_test1 and run_test2 set up the required circuit conditions to test the integrators. run_test1 disconnects the external inputs ise t and vset and applies 2.5 v dc from the reference, simultaneously , to both of the cc and cv. run_test2 has three positions : run , test_cc , and test_cv . loop compensation the AD8451 - e va l z is suita ble for use as a test platform for system loop compensation experiments. however, before installing the platform in a system, c omponent changes are necessary. note the f our compensation networks , cc - charge, cc - discharge, cv - charge , and cv - discharge , locate d on the right - hand side of the schematic shown in figure 52 . to make it easier to locate these components, the configuration of these networks on the AD8451 - e va l z pcb app roximates that shown in the schematic (see figure 52) . each of the components locations accommodates both standard , 1206 size , surface - mount chip resistors and capacitors or leaded components inserted into the pairs of tp thr u hol es spanning the sm footprints. the tp holes accept the popular 0.025 test pins if leaded device s are preferred for multiple loop tests. as shipped, cc and cv loop amplifier filters are configured as voltage followers by replacing feedback capacitors to th e inverting inputs with resistors, and removing the dc coupling resistors from the ia and da outputs. the feedback loops must be reconfigured to close the loops to operate as precision feedback loops. loop compensation requires knowledge of the output dc - t o - dc power converter. it is assumed that the AD8451 is most often used with a switching converter. the scope and breadth of this switching converter design architecture is quite broad, and a thorou gh discussion of all the types and variants of this type of converter is well beyond the scope of this data. when the circuit and component details of the power converter are known, proceed with a calculation of the loop parameters and components , and the values necessary to achieve loop compensation. because the loop is of the type proportional/integrating (pi), a direct dc path is required from the ia and da amplifiers to the error inputs of the cc and cv loop amplifiers. i nstall these resistors at the r1 , r6, r7, r11 , and r12 locations . likewise, the cc and cv amplifiers must be reconfigured from voltage followers to integrators by replacing the 0 ? capacitors at c6, c10, c11, c19 , and c24 with appropriate capacitor s. rev. 0 | page 27 of 32
AD8451 data sheet schematic and artwor k 12137-052 ? 5 v tpisvp rgp ? 5 v c 20 1 f 50 v ? 5 v 2 . 5 c 5 10 f 10 v tpisrefls tpbvns tpbvmea nc bvn nc 25 v tpbvrefh tpbrefl tpbvrefls c 21 1 f 50 v disc h vset tpvsetbf tpiset ismea c 9 0 . 1 f 50 v isvp tpisrefh isvn nc isrefl 25 v tpbv n bv p brefh bvps nc brefl bvp nc nc bvns brefls nc nc nc bvmea bvn nc vref agnd avee avcc mode isvp rgp nc nc nc nc nc nc nc nc nc nc nc nc nc rgn isvn nc 17 18 15 16 8 7 6 5 4 3 2 14 13 9 12 11 10 19 1 20 59 54 56 60 53 51 49 44 43 41 50 58 46 45 47 55 57 52 48 42 vctrl vcln vve 1 vint vclp vve 0 vvp 0 vset nc nc nc nc vsetbf vre f dgn d dvc c n c avc c n c n c 25 v 5 v vctrl 5 v tpvctrl tpvclp 37 40 39 38 34 36 35 21 24 23 22 25 28 27 26 30 33 32 31 29 rgn tpisvn c 18 10 f 10 v c 19 10 f 10 v 80 64 62 69 65 68 67 73 71 78 74 77 76 79 66 75 72 70 61 63 gn d _ bv p gn d _ bv n ex t nor m isreflo 2 . 5 v ex t isrefhi tpmode tpisrefl nc nc nc isrefh nc vref isrefls isrefl nc ive 1 ismea ive 0 iset vint isrefb nc nc agnd avee avcc nc avee 1 2 3 1 2 3 AD8451 x1 tpbvp mod e cv - discharge tp 49 tp 41 tp 61 tp 55 tp 14 tp 54 c 10 * 0 1206 c 14 tbd 1206 r 4 10 k 1206 r 1 tbd 1206 cc - discharge iv e 0 tp 48 tp 40 c 3 tbd 1206 tp 1 tp 53 r 3 10 k 1206 tp 11 tp 13 c 6 * tbd 1206 1206 cc - charge vint tiv e 1 tp 58 tp 62 tp 43 tp 51 r 5 10 k 1206 r 6 tbd 1206 c 11 * 0 1206 c 15 tbd 1206 tp 46 tp 57 tp 6 tp 3 tp 42 tp 50 tvve 1 tp 45 tp 18 tp 56 tp 19 c 24 * 0 1206 r 15 10 k 1206 c 17 tbd 1206 r 14 10 k 1206 tp 26 tp 25 r 12 tbd 1206 tp 23 tp 24 tp 30 tp 33 c 23 tbd 1206 cv - charge bvmea vvp 0 tp 12 tp 4 r 13 10 k 1206 r 11 tbd 1206 c 22 tbd 1206 r 2 10 k 1 % 1206 tp 36 tp 7 r 7 tbd 1206 tp 8 tp 15 tp 9 tp 28 c 2 tbd 1206 tp 16 tp 37 tp 2 tp 5 tp 10 tp 29 c 1 tbd 1206 r 8 10 k 1 % 1206 tpisref b nc nc 2 . 5 5 v + 5 v + c 4 10f 35v + avee + c 8 10f 35v c 7 10f 35v avcc ? 5 v dvcc 25 v vint tpvcln gnd 5 gnd 4 gnd 3 gnd 2 gnd 10 gnd 6 gnd 7 gnd 1 tp _ bvp tp 32 tp 35 tp 39 tp 27 tp 59 tp 47 c 13 tbd 1206 tp 60 c 19 * 0 1206 r 9 10 k 1206 tp 52 tp 44 tp 63 ? 5 v gnd 8 gnd 9 vve 0 tp 17 tp 38 r 10 10 k 1206 tp 31 tp 34 c 12 tbd 1206 vvp 0 5 v ch g 1 2 3 vsetbf r 17 0 ? r 16 0 ? r 18 1 k ? cr 1 5 . 1 v r 19 1 k ? ru n tes t 4 5 6 1 2 3 vset run _ test 1 iset vset 2 1 4 3 vint tvv e 1 vv e 1 6 8 5 7 run _ test 2 vv e 1 tvv e 1 ru n t _ c c t _ c v cr 3 5 . 1 v r 19 1 k ? cr 2 5 . 1 v tpismea j p 1 dvccret aveeret avccret jp 1 bvmea *0? 1206 resis t ors are temporari l y ins t alled in loc a tions c6, c14, c17, c15, and c19. see text for further explan a tion. figure 52 . AD8451 - evalz schematic rev. 0 | page 28 of 32
data sheet AD8451 12137-053 figure 53 . AD8451 - evalz top silks creen 12137-054 figure 54 . AD8451 - evalz primary side copper rev. 0 | page 29 of 32
AD8451 data sheet 12137-055 figure 55 . AD8451 - evalz secondary side copper 12137-056 figure 56 . AD8451 - evalz power plane rev. 0 | page 30 of 32
data sheet AD8451 12137-057 figure 57 . AD8451 - evalz ground plane rev. 0 | page 31 of 32
AD8451 data sheet outline dimensions compliant t o jedec s t andards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 t op view (pins down) pin 1 051706- a figure 58 . 80 - lead low profile quad flat package [ lqfp ] (st - 80 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad845 1 astz ? 40c to + 85c 80- lead lqfp st -80- 2 AD8451 astz - rl ?40c to +85c 80- lead lqfp st -80- 2 AD8451 - evalz evaluation board 1 z = rohs compliant part. ? 2014 analog devices, inc. all rights reserved. trademarks and registered tradema rks are the property of their respective owners. d12137 - 0 - 3/14(0) rev. 0 | page 32 of 32

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